- GRAYBYTE UNDETECTABLE CODES -

403Webshell
Server IP : 184.154.167.98  /  Your IP : 18.221.157.203
Web Server : Apache
System : Linux pink.dnsnetservice.com 4.18.0-553.22.1.lve.1.el8.x86_64 #1 SMP Tue Oct 8 15:52:54 UTC 2024 x86_64
User : puertode ( 1767)
PHP Version : 7.2.34
Disable Function : NONE
MySQL : OFF  |  cURL : ON  |  WGET : ON  |  Perl : ON  |  Python : ON  |  Sudo : ON  |  Pkexec : ON
Directory :  /usr/src/kernels/4.18.0-553.22.1.lve.1.el8.x86_64/drivers/hwspinlock/

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Current File : /usr/src/kernels/4.18.0-553.22.1.lve.1.el8.x86_64/drivers/hwspinlock/Kconfig
# SPDX-License-Identifier: GPL-2.0
#
# Generic HWSPINLOCK framework
#

menuconfig HWSPINLOCK
	bool "Hardware Spinlock drivers"

config HWSPINLOCK_OMAP
	tristate "OMAP Hardware Spinlock device"
	depends on HWSPINLOCK
	depends on ARCH_OMAP4 || SOC_OMAP5 || SOC_DRA7XX || SOC_AM33XX || SOC_AM43XX
	help
	  Say y here to support the OMAP Hardware Spinlock device (firstly
	  introduced in OMAP4).

	  If unsure, say N.

config HWSPINLOCK_QCOM
	tristate "Qualcomm Hardware Spinlock device"
	depends on HWSPINLOCK
	depends on ARCH_QCOM
	select MFD_SYSCON
	help
	  Say y here to support the Qualcomm Hardware Mutex functionality, which
	  provides a synchronisation mechanism for the various processors on
	  the SoC.

	  If unsure, say N.

config HWSPINLOCK_SIRF
	tristate "SIRF Hardware Spinlock device"
	depends on HWSPINLOCK
	depends on ARCH_SIRF
	help
	  Say y here to support the SIRF Hardware Spinlock device, which
	  provides a synchronisation mechanism for the various processors
	  on the SoC.

	  It's safe to say n here if you're not interested in SIRF hardware
	  spinlock or just want a bare minimum kernel.

config HWSPINLOCK_SPRD
	tristate "SPRD Hardware Spinlock device"
	depends on ARCH_SPRD
	depends on HWSPINLOCK
	help
	  Say y here to support the SPRD Hardware Spinlock device.

	  If unsure, say N.

config HSEM_U8500
	tristate "STE Hardware Semaphore functionality"
	depends on HWSPINLOCK
	depends on ARCH_U8500
	help
	  Say y here to support the STE Hardware Semaphore functionality, which
	  provides a synchronisation mechanism for the various processor on the
	  SoC.

	  If unsure, say N.

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